Current Issue : July - September Volume : 2015 Issue Number : 3 Articles : 4 Articles
To minimize energy consumption of a digital circuit, logic can be operated at\nsub- or near-threshold voltage. Operation at this region is challenging due to device and\nenvironment variations, and resulting performance may not be adequate to all applications.\nThis article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage.\nBoth CPUs are placed on the same die and manufactured in 28 nm CMOS process. They\nemploy timing-error prevention with clock stretching to enable operation with minimal\nsafety margins while maximizing performance and energy efficiency at a given operating\npoint. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds\nto 39% energy saving compared to operation based on static signoff timing....
Modern systems-on-chip (SoCs) today contain hundreds of cores, and this\nnumber is predicted to reach the thousands by the year 2020. As the number\nof communicating elements increases, there is a need for an efficient, scalable and\nreliable communication infrastructure. As technology geometries shrink to the deep\nsubmicron regime, however, the communication delay and power consumption of global\ninterconnections become the major bottleneck. The network-on-chip (NoC) design\nparadigm, based on a modular packet-switched mechanism, can address many of the\non-chip communication issues, such as the performance limitations of long interconnects and\nintegration of large number of cores on a chip. Recently, new communication technologies\nbased on the NoC concept have emerged with the aim of improving the scalability limitations\nof conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs) use\nthe radio medium for reducing the performance and energy penalties of long-range and\nmulti-hop communications. As the radio medium can be accessed by a single transmitter\nat a time, a radio access control mechanism (RACM) is needed. In this paper, we present a\nnovel RACM, which allows one to improve both the performance and energy figures of the\nWiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown\nthe effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture....
The accuracy of the lifetime calculation approach of IGBT power modules used in hybrid-electric power trains suffers greatly from\nthe inaccurate knowledge of application typical load-profiles. To verify the theoretical load-profiles with data from the field this\npaper presents a concept to record all junction temperature cycles of an IGBTpower module during its operation in a test vehicle. For\nthis purpose the IGBT junction temperature is measured with a modified gate driver that determines the temperature sensitive IGBT\ninternal gate resistor by superimposing the negative gate voltage with a high-frequency identification signal. An integrated control\nunit manages the TJ measurement during the regular switching operation, the exchange of data with the system controller, and\nthe automatic calibration of the sensor system. To calculate and store temperature cycles on a micro controller an online Rain flow\ncounting algorithm was developed.The special feature of this algorithm is a very accurate extraction of lifetime relevant information\nwith a significantly reduced calculation and storage effort. Until now the recording concept could be realized and tested within a\nlaboratory voltage source inverter. Currently the IGBT driver with integrated junction temperature measurement and the online\ncycle recording algorithm is integrated in the voltage source inverter of first test vehicles. Such research will provide representative\nload-profiles to verify and optimize the theoretical load-profiles used in today�s lifetime calculation....
Thermal sensors (TS) are essential for achieving optimized performance and\nreliability in the era of nanoscale microprocessor and system on chip (SoC). Compiling\nwith the low-power and small die area of the mobile computing, the presented TS supports\na wide range of sampling frequencies with an optimized power envelope. The TS supports\nup to 45 K samples/s, low average power consumption, as low as 20 W, and small core Si\narea of 0.013 mm2. Advanced circuit techniques are used in order to overcome process\nvariability, ensuring inaccuracy lower than �±2 �°C without any calibration. All this makes\nthe presented thermal sensor a cost-effective, low-power solution for 22 nm nanoscale\ndigital process technology....
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